VL3411 HDL Programming Laboratory Syllabus:

VL3411 HDL Programming Laboratory Syllabus – Anna University Regulation 2021

COURSE OBJECTIVES:

● To learn Hardware Description Language (System Verilog).
● To learn the fundamental principles of Digital System Design using HDL and FPGA.
● To learn the fundamental principles of VLSI circuit design in digital domain
● To provide hands on design experience with EDA platforms.

LIST OF EXPERIMENTS:

1. Study of programming with SystemVerilog
• Write the HDL program in Behavioral and Structural modeling (Full adder using half adder)
• Demonstrate Arrays and Queues, Task and Functions, Process Control.
• Demonstrate Random sequence generation, Immediate and Concurrent
assertions.
2. Write the HDL program for the following circuits. Perform functional verification, Synthesis and implement using FPGA
• Basic combinational circuits (Logic Gates, 4×1 Multiplexer, 1×4
Demultiplexer, 4×2 Encoder, 2×4 Decoder.
• Sequential circuits (D, T, JK, SR Flip-flops)
• 4-bit synchronous up/down counter
• 4-bit Asynchronous up/down counter
• Universal Shift Register
• Finite State Machine (Moore/Mealy)
3. Write the HDL program for the following circuits using SystemVerilog. Verify using SystemVerilog assertions and perform post synthesis timing simulation.
• Adder (Min 8 Bit) (Binary adder, Ripple carry adder, Carry look ahead adder)
• Multiplier (Min 8 Bit) (Array multiplier, Carry save multiplier, Booth Multiplier, Wallace tree multiplier)
• Shift Registers (SISO, SIPO, PISO, PIPO)
• Memories (RAM, ROM)

COURSE OUTCOMES:

On completion of the course, students will be able to:
CO1: Write HDL code for basic as well as advanced digital integrated circuit
CO2: Import the logic modules into FPGA Boards
CO3: Synthesize Place and Route the digital Ips
CO4: Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDA tools
CO5: Test and Verification of IC design

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