CEC361 Validation and Testing Technology Syllabus:

CEC361 Validation and Testing Technology Syllabus – Anna University Regulation 2021

COURSE OBJECTIVES:

● Getting familiar with various IC technology.
● Learn MOS theory and testing
● Learn CMOS circuit theory and testing
● Getting expertise on CMOS characterization.
● Explore circuit and device level testing methods

UNIT I TECHNOLOGY INTRODUCTION

Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS Technologies. VLSI Fabrication, Oxidation, Lithography, Diffusion, Ion Implantation, Metallization, Integrated Resistors and Capacitors.

UNIT II MOS THEORY ANALYSIS-I

Basic Electrical Properties of MOS Circuits: Ids-Vds Relationships, MOS Transistor Threshold Voltage Vth, gm, gds, Figure of Merit ωo, Short Channel and Narrow Channel Width Effects.

UNIT III MOS THEORY ANALYSIS- II

Pass Transistor, Transmission Gate, NMOS Inverter, Various Pull-ups, CMOS Inverter Analysis and Design, Bi-CMOS Inverters, Latch up in CMOS Circuits.

UNIT IV CMOS CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION

Sheet Resistance RS, conductivity and its Concept to MOS, Area Capacitance Units, Calculations – Delays, Driving Large Capacitive Loads, Delay Estimation, Logical Effort and Transistor Sizing, Power Dissipation, Reliability.

UNIT V BASIC OF SILICON VALIDATION

Need for Testing, Testing at Various Levels, Objectives of Testing – VLSI Test process and Test Equipment – Types of Testing: Functionality Tests, Silicon Debug, Manufacturing Tests, Defect during manufacturing – Fault Modelling, Observability and Controllability, Fault Coverage, Fault Sampling – ATE, Test economics.

30 PERIODS

PRACTICAL EXERCISES: 30 PERIODS

1. MOS TESTING for Ids-Vds Relationships
2. MOSFET testing for threshold voltage like Vth, gate breakdown voltage.
3. Sheet resistivity measurement.
4. Conductivity measurement.
5. Inverter testing
6. Designing of CMOS inverter/ logic gate and testing of delay estimation.

List of equipment needed for a batch of 30 students (3 in a bench):
● Dual channel SMU for MOSFET testing with Test script processor and IV software: 2 nos (one setup for three students)
● Resistivity and Conductivity Setup – #2 setups
● I-V SMU analyser
● Four Point Collinear Resistivity Measurement Setup
● Resistivity samples #2
● Conductivity Samples #2
● Inverter testing setup: power suppy #1, Scope with AFG and power application: #1no
● Xilinx /CAD: 5 no.

COURSE OUTCOMES:

Upon successful completion of the course the student will be able to
CO1: Complete overview to CMOS fabrication process.
CO2: Understand the fundamental concept of MOS FET and testing.
CO3: Explain the concept of MOS theory and analysis.
CO4: To give the student an understanding of CMOS performance testing and estimation.
CO5: Explain the basics of Testing and Fault Modeling

TEXT BOOKS:

1. Kamran Ehraghian, Dauglas A. Pucknell and Sholeh Eshraghiam, “Essentials of VLSI Circuits and Systems” – PHI, EEE, 2005 Edition.
2. Neil H. E. Weste and David. Harris Ayan Banerjee,, “CMOS VLSI Design” – Pearson Education, 1999.

REFERENCES

1. M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2004
2. N.K. Jha and S.G. Gupta, “Testing of Digital Systems”, Cambridge University Press, 2003
3. Etienne Sicard, Sonia Delmas Bendhia, “Basics of CMOS Cell Design”, TMH, EEE, 2005