CEC362 VLSI Testing and Design for Testability Syllabus:

CEC362 VLSI Testing and Design for Testability Syllabus – Anna University Regulation 2021

COURSE OBJECTIVES:

 To introduce logic and fault simulation and testability measures.
 To study the design for testability.
 To know about interfacing and testing of memory
 To introduce power management techniques in testing
 To study testability in analog circuits

UNIT I TEST REQUIREMENTS AND METRICS

Validation platforms- SOC design methodology, IP components, Integration, Clocking, I/Os and interfaces, Device modes, Logic, memories, analog, I/Os, power management; Test requirementsTest handoffs, Testers Where DUT and DFT fit into design / framework; Test- ATPG, DFT, BIST, COF, TTR; Test cost metrics and test economics; Logic fault models- SAF, TDF, PDF, Iddq, StBDG, Dy-BDG, SDD; Basics of test generation and fault simulation- Combinational circuits, Sequential; Specific algorithmic approaches, CAD framework, Optimisations.

UNIT II SCAN DESIGN AND BIST

Scan Design- Scan design requirements, Types of scan and control mechanisms, Test pattern construction for scan, Managing scan in IPs and SOCs, Scan design optimisations, Partitioning, Clocking requirements for scan and delay fault testing, Speed of operation; BIST – Framework, Controller configurations, FSMs, LFSRs, STUMPS architecture, Scan compression and bounds, Test per cycle, Test per scan, Self-testing and self-checking circuits, Online test.

UNIT III MEMORY TEST AND TEST INTERFACES

Memory Test -Memory fault models, Functional architecture as applicable to test, Test of memories, Test of logic around memories, BIST controller configuration, Test of logic around memories, DFT and architecture enhancements, Algorithmic optimisations; Test Interfaces-Test control requirements, Test interfaces – 1500, JTAG, Hierarchical, serial control, Module / IP test, SOC test, Board test, System test, Boundary scan.

UNIT IV DESIGN CONSIDERATIONS AND POWER MANAGEMENT DURING TEST

Design Considerations- Design considerations, Physical design congestion, Partitioning, Clocks, Test modes, Pins, Test scheduling, Embedded test, Architecture improvements, Test in the  presence of security; Power management during test- Methods for low power test, ATPG methods, DFT methods, Scan methods, Low power compression, Test of power management, Implications of power excursions, Optimisations.

UNIT V ANALOG TEST

Test requirements. DFT methods. BIST methods. Test versus measurement. Defect tests versus performance tests. Tests for specific modules – PLL, I/Os, ADC, DAC, SerDes, etc. RF test requirements.

COURSE OUTCOMES:

At the end of this course, the students will be able to:
CO1:Understand logic and fault simulation requirements and testability measures.
CO2:Understand the Design for Testability.
CO3:Develop interfacing and memory testing.
CO4:Perform testing with power management techniques.
CO5 :Carry-out fault Detection in analog circuits.

TEXT BOOK:

1. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits,Vishwani Agrawal and Michael Bushnell, Springer, 2002.

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