CMR357 VLSI and FPGA Syllabus:
CMR357 VLSI and FPGA Syllabus – Anna University Regulation 2021
COURSE OBJECTIVES:
• To introduce the features of programmable logic devices
• To learn the features of various FPGAs and FPAA
• To understand the concepts of synchronous and asynchronous FSMs
• To provide the system design experience with FSMs using PLDs
• To introduce pulse mode approach to asynchronous FSM
UNIT – I PROGRAMMABLE LOGIC DEVICES
Logic implementation options – Technology trends – Design with Field Programmable devices – ROM, PLA, PAL – CPLD – XC9500 family – Erasable Programmable Logic Devices – MAX5000, MAX7000 families.
UNIT – II FPGA AND FPAA
Programming Technology, Logic blocks, routing architectures of SRAM-Programmable FPGA Architectures – XC2000, XC3000, XC4000 – Anti-fuse Programmed FPGAs – Routing Architecture of the Actel FPGAs – ProASIC plus – Design Applications – Current FPGA Technologies – FPAA architecture and its reconfiguration.
UNIT – III SYNCHRONOUS FSM DESIGN
Choice of Components to be Considered – Architecture Centered around Nonregistered PLDs – State Machine Designs – Centered around a Shift Register, Centered around a Parallel Loadable Up/Down Counter – One hot design method – Use of Algorithmic State Machine, Application of one hot design to serial 2’s complementer, parallel to serial adder/subtractor controller- System-level design: controller, data path, and functional partition.
UNIT – IV ASYNCHRONOUS STATE MACHINE DESIGN
Features and need for Asynchronous FSMs – Lumped path delay models for asynchronous FSMs – Excitation table, state diagrams, K-maps, and state tables – Design of the basic cells by using the LPD model – design examples – Hazards in Asynchronous FSMs – One-hot design of asynchronous state machines – Design of fundamental mode FSMs by using PLDs.
UNIT – V PULSE MODE APPROACH TO ASYNCHRONOUS FSM DESIGN
Pulse Mode Models and System Requirements – Choice of Memory Elements – Other Characteristics of Pulse Mode FSMs – Design Examples – Analysis of Pulse Mode FSMs – One-Hot Programmable Asynchronous Sequencers.
TOTAL: 45 PERIODS
COURSE OUTCOMES
Upon successful completion of the course, students should be able to:
CO1: Implement the digital designs with programmable logic devices
CO2: Analyze the architectural features of FPGA and FPAA
CO3: Make the system level designs using synchronous and asynchronous FSMs
CO4: Design the fundamental mode FSMs using PLDs
CO5: Apply pulse mode approach to FSM Design
TEXT BOOKS:
1. Stephen M. Trimberger, Edr.,“Field Programmable Gate Array Technology”, Springer Science Business media, LLC, 2012.
2. Richard F. Tinder, “Engineering Digital Design, Revised Second Edition”, Academic Press, 2000.
REFERENCES:
1. Roger Woods, John McAllister, Gaye Light body and Ying Yi, “FPGA-based implementation of Signal Processing Systems”, A John Wiley and Sons, Ltd., Publication, 2008.
2. John V. Oldfield, Richard C.Dorf, “Field Programmable Gate Arrays – Reconfigurable logic for rapid prototyping and implementation of digital systems”, John Wiley & Sons, Reprint, 2008.
3. P. K .Chan& S. Mourad, “Digital Design Using Field Programmable Gate Array”, Prentice Hall, 1994.
4. Thomas L. Floyd, “Electronic Devices”, Pearson Education Ltd., 8th Edition, 2008.