EI25C08 Digital System Design and Applications Syllabus:

EI25C08 Digital System Design and Applications Syllabus – Anna University UG Syllabus Regulation 2025:

Course Objective:

This course introduces number systems, Boolean algebra, and gate-level minimization for digital logic design. It emphasizes the design and analysis of combinational and sequential logic circuits including both synchronous and asynchronous types. It also covers programmable logic devices, digital simulation, and VHDL-based implementation for practical applications.

Boolean Algebra and Gate Level Minimization

Review of number systems, types and conversion, binary codes, error detection and correction codes (Parity and Hamming code). Boolean theorems and properties, Boolean functions, logic gates. Gate-level minimization using Karnaugh Map, SOP & POS simplification, Don’t care conditions. Implementations of logic functions using gates – NAND, NOR implementations.

Combinational Logic

Design of adders, subtractors, multiplexers. Combinational logic design using multiplexers. Demultiplexers and their use in combinational logic design. 2-bit magnitude comparator, code converters – BCD to Binary and Binary to BCD, encoder, priority encoder – Decimal to BCD, Octal to Binary, decoders – BCD to Decimal and BCD to Seven Segment Display Decoder.

Synchronous Sequential Logic

Sequential logic – SR, JK, JKMS, D and T flip-flops, characteristics and excitation table, level triggering and edge triggering, counters – asynchronous and synchronous type, modulo counters, shift registers. Design of synchronous sequential circuits – Moore and Mealy models, state diagram, state reduction, state assignment.

Asynchronous Sequential Circuits

Asynchronous sequential logic circuits – transition and flow table, race conditions, hazards, and errors in digital circuits, analysis of asynchronous sequential logic circuits.

Memory and Logic Families

Memories: PROM, PLA, PAL, CPLD, FPGA. Digital logic gate realization and characteristics of TTL, ECL, and CMOS families.

VHDL

RTL Design – combinational logic, sequential circuit, operators. Introduction to packages, subprograms, testbench.
(Simulation/Tutorial Examples: adders, counters, flip-flops, multiplexers & demultiplexers)

Tasks:

T1:Apply mathematical knowledge of number systems, Boolean expressions/functions to simplify and realize logical expressions.
T2:Design and verify combinational logic circuits
T3:Design and verify synchronous sequential logic circuits.
T4:Analyze and design asynchronous sequential logic circuits.
T5:Understand memory types and gain knowledge on building blocks of different Programmable Logic devices and make use of appropriate software such as VHDL for electronic prototyping and modeling of digital systems.

Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%.

Assessment Methodology: Assignments (20%), Solution to application-oriented problems using software (20%), Review of GATE questions (20%), Internal Examinations (40%).

References:

1. Bignel, J. W. (2007). Digital electronics (5th ed.). Cengage Learning.
2. Comer. (2016). Digital logic & state machine design (3rd ed.). Oxford.
3. Kamal, R. (2012). Digital systems: Principles and design. Pearson Education India.
4. Keitz, W. (2013). Digital electronics: A practical approach with VHDL. Pearson.
5. Kothari, D. P., & Dhillon, J. S. (2016). Digital circuits and design. Pearson Education.
6. Mandal. (2013). Digital electronics: Principles & application. McGraw Hill.
7. Mano, M., & Ciletti, M. D. (2018). Digital design: With an introduction to the Verilog HDL, VHDL, and System Verilog (6th ed.). Pearson India.

List of Open Source Software / Learning Websites:

1. https://nptel.ac.in/courses/117106114
2. https://nptel.ac.in/courses/117106086
3. https://nptel.ac.in/courses/106102181
4. https://archive.nptel.ac.in/courses/108/105/108105132/
5. https://nptel.ac.in/courses/108106177